This invention relates to the field of digital frequency doublers and more particularly to doublers providing an output having a symmetrical duty cycle for use in a programmable tone generator.
When it is desired to divide a relatively high frequency, e.g. four megahertz, down to a relatively low or audio frequency, it is well known to use the signal as the clock input to a chain or programmable synchronous counters with the appropriate output point coupled back to the "carry-in" input to provide the desired divisor number. However, the output is usually not symmetrical, and it is known to first multiply the original signal by a factor of two, then divide by two after the programmable divider to obtain the symmetrical output.
When the output of the programmable synchronous divider is a series of narrow pulses, and a square wave is needed in order to provide a strong fundamental tone as in the audio range, the narrow pulses of the divider output can be coupled to a bi-stable multivibrator in order to create a square wave. This, however, divides the output frequency by two, and requires doubling the input clock frequency. In certain applications, e.g., the programmable tone generator disclosed in U.S. Pat. No. 3,939,751, and assigned to the assignee of the present invention, an output rich in fundamentals is required for obtaining the musical tones for a musical instrument, and a ripple divider chain was used. When it became desirable to use a synchronous divider, as disclosed in Ser. No. 736,985, filed on Oct. 29, 1976 and assigned to the same assignee, the output of the synchronous divider was required to be processed to obtain the necessary square wave output thus the frequency was divided by two. Since it was economically desirable to continue using the original crystal, a doubler circuit was necessary in order to compensate for the divide-by-two function of the bi-stable multivibrator at the output of the divisor. Since the binary counters of the synchronous programmable divider require a minimum pulse width for proper operation at clock rates above three megahertz, a doubler circuit was needed which provided substantially 50 percent duty cycle output.